1. Field of the Invention
The present invention relates to a solenoid driving circuit for conducting current through a solenoid to drive the solenoid driving a key or a pedal of an automatic performance piano in response to a pulse width modulation signal and more particularly, to a circuit for detecting abnormal conduction of current conducted through the solenoid.
2. Background Art
Circuits for detecting abnormal conduction of current conducted through a solenoid are conventionally known. For example, a circuit (hereafter referred to as detecting circuit (1)) having a design such as that shown in FIG. 6 is available. In the illustrated circuit, an input terminal 1 is provided, to which a pulse width modulation signal is supplied. The input terminal 1 connects to one terminal of an input resister 2. The other terminal of the input resister 2 connects to the base of a switching transistor 3 turned on or off in response to the pulse width modulation signal. The collector of the transistor 3 is connected to one terminal of a solenoid 4, to an anode of a diode 5 and to a cathode of a diode 6. Current is conducted through the solenoid 4 in response to the pulse width modulation signal, whereby the solenoid 4 drives a key or a pedal of an automatic performance piano. The diode 5 is a protector for protecting the solenoid 4. The other terminal of the solenoid 4 connects to a cathode of the diode 5 and a power supply voltage, for example, 100 V is applied thereto. The set of elements 1 through 6 described above is provided in response to the number of keys and pedals, for example, about 90. Diode 6.sub.a through 6.sub.c show that elements 1 through 6 connect to the terminal a in parallel.
The cathode of a diode 7 connects to the terminal a. The anode of the diode 7 connects to a terminal b by which one terminal of resistors 8 and 9 are connected to each other. To the other terminal of resistor 8 a power supply voltage of, for example, 5 V is applied. The other terminal of the resistor 9 connects to the one terminal of a resistor 10. The resistors 9 and 10 divide the voltage appearing in the terminal b. The one terminal of the resistor 10 connects to the one terminal of a resistor 11 and to the anode of a diode 12. The other terminal of the resistor 11 is connected to a cathode of the diode 12, to one terminal of a capacitor 13 and to a pulse input terminal of a comparator 14. The other terminal of the capacitor 13 connects to the earth. Each of elements 11 through 13 described above together form an analog integral circuit having a time constant of approximately a few seconds. A reference voltage V.sub.ref is applied to the minus input terminal of comparator 14. The one terminal of resistor 15 connects to an output terminal of the comparator 14. The resistor 15 is a pull-up resistor and has a power supply voltage of, for example, 5 V applied to its other terminal. An output terminal 16 for the detecting circuit (1) as a whole is provided, output terminal 16 being connected to the output terminal of the comparator 14, as well as with one terminal of resistor 15.
With the detecting circuit (1) as described above, when the pulse width modulation signal as shown in FIG. 7 is supplied to the input terminal 1, the transistor 3 is turned on or off in response to it, whereby the transistor 3 allows the current to be conducted through the solenoid 4 while the pulse width modulation signal supplied to the input terminal 1 is in high state.
Because of the features described in the preceding paragraph, a collector voltage of the transistor 3 is varied as shown in FIG. 8. As a result, until the collector voltage of the transistor 3 decreases to less than 5 V, the diodes 6 and 7 are conductive. Accordingly, the voltage appearing in the terminal b is divided by the resistors 9 and 10, and then, is integrated by the analog integral circuit. The integrated result in the analog integral circuit is compared with the reference voltage V.sub.ref by the comparator 14.
Accordingly, when a voltage appearing in the pulse input terminal of the comparator 14 and corresponding to a conductive state wherein the collector voltage of the transistor 3 is less than 5 V is less than the standard voltage V.sub.ref, an "L" level abnormal conduction detecting signal, indicating abnormal conduction, is output from the output terminal 16.
Next, FIG. 9 illustrates an other conventional circuit (hereafter referred to as detecting circuit (2)) for detecting abnormal conduction of the current conducted through the solenoid. In the illustrated circuit, a pulse width modulation signal generating circuit 17 generates the pulse width modulation signal. The output terminal of the pulse width modulation signal generating circuit 17 connects to one terminal of a resister 18. The other terminal of the resistor 18 connects to one terminal of a resistor 19 and the base of a transistor 20. The resistors 18 and 19 divide the voltage appearing in the output terminal of the pulse width modulation signal generating circuit 17. The transistor 20 connects to a transistor 21 with a darlington connection. The transistors 20 and 21 are turned on or off in response to the pulse width modulation signal. Collectors of the transistors 20 and 21 are connected to one terminal of a solenoid 22, to an anode of a diode 23, to one terminal of a capacitor 24 and to a cathode of a diode 25. Current is conducted through the solenoid 22 in response to the pulse width modulation signal, whereby the solenoid 22 drives a key or a pedal of an automatic performance piano. The diode 23 is a protector for protecting the solenoid 22. The capacitor 24 is a noise reducer for reducing noise generated in the solenoid 22. The other terminal of the solenoid 22 connects to a cathode of the diode 23 and to tile other terminal of the capacitor 24, and a power supply voltage V.sub.DD is applied thereto. The set of elements 17 through 25 described above is provided In response to the number of keys and pedals, for example, about 90. Diode 25.sub.a through 25.sub.c indicate that elements 17 through 25 are connected to the terminal b in parallel.
An cathode of a diode 26 connects to the terminal b. The anode of the diode 26 connects to one terminal of resistor 27. The other terminal of the resistor 27 connects to a terminal c via which one terminal of resistors 28 and 29 are connected to each other. A power supply voltage V.sub.cc is applied to the other terminal of resistor 28. The terminal c connects to one terminal of a resistor 30 and to the anode of a diode 31. The other terminal of the resistor 30 connects to the cathode of the diode 31, to one terminal of a capacitor 32 and to a pulse input terminal of a comparator 33. The other terminal of the capacitor 32 connects to the earth. Each of elements 30 through 32 described above together form an analog integral circuit having a time constant of approximately a few seconds. A power supply voltage V.sub.cc is applied to one terminal of the resistor 34. The other terminal of resistor 34 is connected to one terminal of a resistor 35 and to one terminal of a capacitor 36. The resistors 34 and 35 divide the power supply voltage V.sub.cc. The other terminal of the capacitor 36 connects to the earth. The result voltage divided by the resistors 34 and 35, namely, a reference voltage V.sub.ref, is applied to the minus input terminal of comparator 33. An output terminal 37 for the detecting circuit (2) as a whole is provided, and is connected to an output terminal of the comparator 33.
The value of the resistor 27 is, for example, designed to be about a hundredth of the value of the resistor 29; the value of the resistor 28 is, for example, designed to be about a twentieth of the value of the resistor 29; and the value of the resistor 30 is, for example, designed to be about twice of the value of the resistor 29.
In this case, the power supply voltage V.sub.DD and V.sub.cc are designed to be 120 V and 5 V, respectively, and the value of the resistors 27 through 30, 34 and 35 are designed to be 1 k.OMEGA., 4.7 k.OMEGA., 100 k.OMEGA., 220 k.OMEGA., 12 k.OMEGA. and 10 k .OMEGA., respectively. The value of the capacitor 32 is designed to be 10 .mu.F.
With the detecting circuit (2) as described above, when a pulse width modulation signal is generated by the pulse width modulation signal generating circuit 17, the transistors 20 and 21 are turned on or off in response to it and the transistors 20 and 21 thereby allow the current to conduct through the solenoid 22 while the pulse width modulation signal is in high state.
In this case, because electric potential at terminal a, namely, collector electric potential of the transistor 21, becomes approximately equal to the value of the power supply voltage V.sub.DD (120 V), and electric potential at terminal c becomes approximately equal to the result value of the power supply voltage V.sub.cc (5 V) divided by the resistors 28 and 29 that is about 4.78 V while the transistor 21 is turned off, the diodes 25 and 26 become nonconductive.
Accordingly, in response to electric potential across both ends of the resistor 28, the diode 31 and the capacitor 32 are serially-connected, that is, in response to the power supply voltage V.sub.cc (5 V), electric charge is accumulated in the capacitor 32. In this case, charge time is approximately equal to the time constant determined by the value of the resistor 28 and the capacitor 32, respectively.
In contrast, because the electric potential at terminal namely, the collector electric potential of the transistor 21, becomes approximately equal to 0 V, but the electric potential at terminal c remains unchanged, approximately equal to the result value of the power supply voltage V.sub.cc (5 V) divided by the resistors 28 and 29, that is, about 4.78 V while the transistor 21 is turned on, the diodes 25 and 26 become conductive.
Accordingly, because the electric potential at terminal c becomes approximately equal to the result value of the power supply voltage V.sub.cc (5 V) divided by the resistors 27 and 28, that is, about 0.87 V, electric charge in the capacitor 32 while the transistor 21 is turned off is discharged via the resistors 30 and 27, the diodes 26 and 25 and the transistor 21. In this case, discharge time is approximately equal to the time constant determined by the value of the resistor 30 and the capacitor 32, respectively.
In the normal case, since the charge and discharge operation in the capacitor 32 described above are alternately repeated in response to the pulse width modulation signal from the pulse width modulation signal generating circuit 17, the electric potential of the capacitor 32 is always higher than the predetermined reference voltage V.sub.ref (about 2.7 V). Consequently, a signal representative of the normal conduction of the current conducted through the solenoid 22 is supplied to the output terminal 37 in high state.
However, if, for whatever reason, short state or turn-on state in the transistor 21 continues, namely tile current continues conducting through the solenoid 22 for long time, since tile discharge time of the capacitor 32 becomes longer than in normal state, the electric potential of the capacitor 32 becomes lower than the reference voltage V.sub.ref. Consequently, the abnormal conduction detecting signal, indicating the abnormal conduction of the current conducted through the solenoid 22, is supplied to the output terminal 37 in low state.
Thus, the controlling circuit (not shown) is supplied with tile abnormal conduction detecting signal and stops permitting the current to conduct through the solenoid 22 and thereby prevents burning of the solenoid 22.
Since the above-mentioned conventional detecting circuit (1) consists of analog discrete components, the number of components is large, and it is difficult to miniaturize the conventional detecting circuit (1). Moreover, detection accuracy of the conventional detecting circuit (1) is affected by the accuracy of the time constant of the analog integrated circuit. In the conventional detecting circuit (1), even if the current conducts through the solenoid 4, if the collector voltage of the transistor 3 does not decrease to less than 5 V the abnormal conduction of the current conducted through the solenoid 4 is not detected. Consequently, a disadvantageous is presented in that when the abnormal conduction of the current through solenoid 4 is detected, the transistor 3 has already broken down or the solenoid 4 has already burned due to continuous current conduction through it.
In contrast, in the above-mentioned conventional detecting circuit (2), a short state, wherein the turn-on state of the transistor 21 is continuous or the collector-emitter voltage V.sub.CE has reached on 0-1.5 V, is detected, and the abnormal conduction detecting signal is output.
However, there is among the failure modes of the transistor 21 one wherein a half short state occurs between the collector-emitter. Because the conventional circuits cannot detect this state, the solenoid 22 burns, this being a serious disadvantage in the conventional art.
Furthermore, in the automatic performance piano using the conventional detecting circuit (2), the situation can occur where the power for the automatic performance plano as a whole remains on and unchanging, but the power supply voltage V.sub.DD applied to the solenoid 22 is turned off when the action of the automatic performance piano is stopped.
However, in the conventional detecting circuit (2), since the state where the power supply voltage V.sub.DD applied to the solenoid 22 is turned off is identical to the state where the transistor 21 is turned on as circuit action, the electric charge in the capacitor 32 is discharged via the resistors 30 and the diodes 26 and 25 and the transistor 21. Consequently, because the electric potential of the capacitor 32 is also lower than the reference voltage V.sub.ref in this case, the abnormal conduction detecting signal is supplied to the output terminal 37 in low state.